Description

Farsince 400G QSFP‑DD to 2×200G QSFP56 passive breakout is a twinax assembly that splits one 400G port into two independent 200G copper links. The QSFP‑DD end carries eight 50G PAM4 lanes and maps them as two groups of 4×50G PAM4 to the QSFP56 plugs. It provides a straightforward way to distribute a 400G uplink to dual 200G devices—such as servers, accelerators and switch downlinks—across short distances in AI clusters, HPC fabrics and leaf/spine networks.

With no active components, the DAC adds near‑zero latency and draws only minimal ID current from the host. Controlled‑impedance pairs, full shielding and robust overmold ensure low insertion loss and crosstalk, while a 39.5 mm minimum bend radius supports tidy routing in dense racks. The assembly is hot‑pluggable and interoperable with platforms following QSFP‑DD and QSFP56 MSA mechanics and IEEE 802.3 electrical specifications. Farsince supports vendor‑specific coding, custom lengths and labeling, and provides batch test reports to simplify volume deployment and maintenance.

Specifications

• Product Type: 400G to 2×200G Passive Direct Attach Copper Breakout
• Host Interface: QSFP‑DD, 8×50G PAM4
• Device Interface: 2× QSFP56, each 4×50G PAM4 (200G)
• Cable Direction: QSFP‑DD to dual QSFP56 fan‑out
• Data Rate: 400 Gbps aggregate; 2×200 Gbps legs
• Wire Gauge: 28 AWG
• Cable Structure: Shielded twinax harness, passive copper
• Minimum Bend Radius: 39.5 mm
• Power Design: Passive; ≤0.1 W per end for ID/EEPROM
• Installation: Hot‑pluggable connectors with pull‑tab latch
• Application: In‑rack switch‑to‑server/accelerator fan‑out for AI/HPC and data centers
• Compatibility: IEEE 802.3cd; QSFP‑DD & QSFP56 MSA; SFF‑8636/8679 memory maps
• Compliance: RoHS, REACH
• Customization: Vendor coding, length and labeling options; test reports available