Description

This assembly routes a full‑bandwidth PCI Express 5.0 x16 connection from dual MCIO (SFF‑TA‑1002) board ports to a remote PCIe x16 card slot. It is designed for servers and accelerator platforms where GPUs, AI cards or FPGA adapters must be relocated for thermals or mechanical layout. Each MCIO plug carries eight lanes; two plugs combine to deliver a 16‑lane, 32 GT/s link to the detachable x16 slot module. The harness integrates high‑speed twinax conductors with full shielding and a braided jacket, while the slot module provides a robust card connector with mechanical retention for stable operation in chassis environments.

Engineered for cable PCIe, the assembly preserves reference clock and sideband control and is backward compatible with PCIe Gen4/Gen3. It enables flexible GPU placement, improved airflow and easier service in dense servers or edge systems. Farsince supports project‑specific lengths, slot orientations and mounting brackets, and can tune equalization/trace impedance to match host requirements. Each cable is electrically tested for continuity and lane mapping to help ensure link training at Gen5 rates.

Specifications

• Product Type: PCIe Gen5 x16 riser/extension cable assembly
• Host Interface: 2 × MCIO SFF‑TA‑1002 (x8 each)
• Device Interface: PCIe x16 card slot (edge connector)
• Cable Direction: Dual MCIO host to remote x16 slot
• Data Rate: PCIe 5.0, 32 GT/s; backward compatible with Gen4/Gen3
• Application: Remote GPU/AI accelerator, FPGA, RAID/NIC add‑in cards
• Cable Structure: Shielded high‑speed twinax with braided jacket
• Signal Support: PCIe lanes, REFCLK, PERST#, sideband and presence
• Length Options: Customizable per project
• Installation: Remote slot module with mounting features for chassis integration
• Power Design: Pass‑through 12 V from host slot; external GPU power cables required for high‑power cards
• Standards: PCI Express 5.0, SFF‑TA‑1002
• Compatibility: Works with MCIO‑equipped server/mainboard platforms
• Compliance: RoHS, REACH
• Customization: Length, pin mapping, bracket type, labeling and acceptance testing