Description

Farsince 200G QSFP56 passive breakout DAC is a copper twinax harness that splits one 200G QSFP56 port into two independent 100G QSFP56 connections. The assembly carries four 50G PAM4 lanes on the host side and maps them as two groups of 2×50G PAM4 to the device ends. It provides a straightforward way to utilize a 200G uplink for dual 100G downlinks between switches, GPU nodes and servers in leaf/spine fabrics, AI clusters and equipment rooms where short‑reach, predictable connectivity is required.

With no active components, the passive design adds virtually no latency and draws only a small ID current from the host. Controlled‑impedance copper and comprehensive shielding maintain low insertion loss and crosstalk, while a compact 30 mm minimum bend radius supports neat routing in dense racks. The cable is hot‑pluggable and interoperable with platforms that follow QSFP56 MSA and IEEE 802.3cd electrical specifications. Farsince can supply vendor‑specific coding, custom lengths and labeling, and batch test documentation to streamline deployment and maintenance at scale.

Specifications

• Product Type: 200G to 2×100G Passive Direct Attach Copper Breakout
• Host Interface: QSFP56, 4×50G PAM4
• Device Interface: 2× QSFP56, each 2×50G PAM4 (100G)
• Data Rate: 200 Gbps aggregate; 2×100 Gbps legs
• Modulation/Lane Mapping: 4×50G PAM4 to 2×(2×50G PAM4)
• Wire Gauge: 26 AWG
• Cable Structure: Shielded twinax harness, passive copper
• Minimum Bend Radius: 30 mm
• Power Consumption: ≤0.1 W per end (host 3.3 V for ID)
• Jacket Material: PVC (OFNR)
• Application: Fan‑out from 200G switch to two 100G ports in AI/HPC and data centers
• Compatibility: IEEE 802.3cd; QSFP56 MSA; SFF‑8665 cage; SFF‑8636 memory map
• Compliance: RoHS, REACH
• Customization: Vendor coding, length and labeling options; test reports